module Instruction_Register(iInstructionIn, oInstructionOut, iIRWrite, iReset, iClk);
	input [31:0] iInstructionIn;
	input iIRWrite, iReset, iClk;
	output [31:0] oInstructionOut;
	reg [31:0] oInstructionOut;

	always @(posedge iReset or posedge iClk)
	begin
		if(iReset)
			oInstructionOut <= 32'b0;
		else if(iIRWrite)
			oInstructionOut <= iInstructionIn;
		else
			oInstructionOut <= oInstructionOut;
	end
	
endmodule